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ds092 (v1.2) may 13, 2002 www.xilinx.com 1 advance product specification 1-800-255-7778 ? 2002 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? optimized for 1.8v systems - as fast as 4.0 ns pin-to-pin logic delays - as low as 15 a quiescent current - 64 macrocells with up to 1,600 logic gates - fast input registers - slew rate control on individual outputs - lvcmos 1.8v through 3.3v - 1.5v i/o compatible - lvttl 3.3v available in multiple package options - 44-pin plcc with 33 user i/o - 44-pin vqfp with 33 user i/o - 56-ball cp bga with 45 user i/o - 100-pin vqfp with 64 user i/o advanced system features - fastest in system programming 1.8v isp using ieee 1532 (jtag) interface - ieee1149.1 jtag boundary scan test - optional schmitt-trigger input (per pin) - fast zero power? (fzp) 100% cmos product term generation - flexible clocking modes optional dualedge triggered registers - global signal options with macrocell control multiple global clocks with phase selection per macrocell multiple global output enables global set/reset - efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks - advanced design security - open-drain output option for wired-or and led drive - optional configurable grounds on unused i/os - mixed i/o voltages compatible with 1.5v, 1.8v, 2.5v, and 3.3v logic levels - pla architecture superior pinout retention 100% product term routability across function block - hot pluggable refer to the coolrunner?-ii family data sheet for architec- ture description. description the coolrunner-ii 64-macrocell device is designed for both high performance and low power applications. this lends power savings to high-end communication equipment and high speed to battery operated devices. due to the low power stand-by and dynamic operation, overall system reli- ability is improved this device consists of four function blocks inter-con- nected by a low power advanced interconnect matrix (aim). the aim feeds 40 true and complement inputs to each function block. the function blocks consist of a 40 by 56 p-term pla and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. additionally, these registers can be globally reset or preset and configured as a d or t flip-flop or as a d latch. there are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. a schmitt trigger input is available on a per input pin basis. in addition to stor- ing macrocell output states, the macrocell registers may be configured as "fast input" registers to store signals directly from input pins. clocking is available on a global or function block basis. three global clocks are available for all function blocks as a synchronous clock source. macrocell registers can be individually configured to power up to the zero or one state. a global set/reset control line is also available to asynchro- nously set or reset selected registers during operation. additional local clock, synchronous clock-enable, asyncho- nous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-function block basis. a dualedge flip-flop feature is also available on a per mac- rocell basis. this feature allows high performance synchro- nous operation based on lower frequency clocking to help reduce the total power consumption of the device. the coolrunner-ii 64-macrocell cpld is i/o compatible with standard lvttl and lvcmos18, lvcmos25, and lvcmos33 (see ta b le 1 ). this device is also 1.5v i/o com- patible with the use of schmitt-trigger inputs. 0 xc2c64 coolrunner-ii cpld ds092 (v1.2) may 13, 2002 00 advance product specification r
xc2c64 coolrunner-ii cpld 2 www.xilinx.com ds092 (v1.2) may 13, 2002 1-800-255-7778 advance product specification r fast zero power design technology xilinx coolrunner-ii cplds are fabricated on a 0.18 micron process technology which is derived from leading edge fpga product development. coolrunner-ii cplds employ fast zero power? (fzp), a design technique that makes use of cmos technology in both the fabrication and design methodology. fzp design technology employs a cascade of cmos gates to implement sum of products instead of tradi- tional sense amplifier methodology. due to this technology, xilinx coolrunner-ii cplds achieve both high performance and low power operation. supported i/o standards the coolrunner-ii 64 macrocell features both lvcmos and lvttl i/o implementations. see ta b l e 1 for i/o stan- dard voltages. the lvttl i/o standard is a general purpose eia/jedec standard for 3.3v applications that use an lvttl input buffer and push-pull output buffer. the lvcmos standard is used in 3.3v, 2.5v, 1.8v applications. coolrunner-ii cplds are also 1.5v i/o compatible with the use of schmitt-trigger inputs. table 1: i/o standards for xc2c64 i/o types output v ccio input v ccio input v ref board termination voltage v t lvttl 3.3 3.3 n/a n/a lvcmos33 3.3 3.3 n/a n/a lvcmos25 2.5 2.5 n/a n/a lvcmos18 1.8 1.8 n/a n/a 1.5v i/o 1.5 1.5 n/a n/a figure 1: i cc vs frequency table 2: i cc vs frequency (lvcmos 1.8v t a = 25c) (1) frequency (mhz) 0 25 50 75 100 150 175 200 225 250 270 typical -5, -7.5 i cc (ma) 0.015 1.85 3.69 5.55 7.35 10.87 12.54 14.22 15.91 17.56 18.9 typical -4 i cc (ma) notes: 1. 16-bit up/down, resettable binary counter (one counter per function block). frequency (mhz) ds092_01_030102 i cc (ma) 0 0 5 10 15 20 300 250 200 150 100 -5, -7.5 50
xc2c64 coolrunner-ii cpld ds092 (v1.2) may 13, 2002 www.xilinx.com 3 advance product specification 1-800-255-7778 r recommended operating conditions dc electrical characteristics (over recommended operating conditions) absolute maximum ratings symbol description value units v cc supply voltage relative to ground ?0.5 to 2.0 v v ccio supply voltage for output drivers ?0.5 to 4.0 v v jtag jtag input voltage limits ?0.5 to 4.0 v v aux jtag input supply voltage ?0.5 to 4.0 v v in input voltage relative to ground (1) ?0.5 to 4.0 v v ts voltage applied to 3-state output (1) ?0.5 to 4.0 v t stg storage temperature (ambient) ?65 to +150 c t sol maximum soldering temperature (10s @ 1/16in. = 1.5mm) +260 c t j junction temperature +150 c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easiest to achieve. during transitions, the device pins may undershoot to ?2.0v or overshoot to +4.5v, provided this over or undershoot lasts less than 10 ns and with t he forcing current being limited to 200 ma. symbol parameter min max units v cc supply voltage for internal logic and input buffers commercial t a = 0c to +70c 1.7 1.9 v industrial t a = ?40c to +85c 1.7 1.9 v v ccio supply voltage for output drivers @ 3.3v operation 3.0 3.6 v supply voltage for output drivers @ 2.5v operation 2.3 2.7 v supply voltage for output drivers @ 1.8v operation 1.7 1.9 v supply voltage for output drivers @ 1.5v operation 1.4 1.6 v v aux jtag programming pins 1.7 3.6 v symbol parameter test conditions min. max. units i ccsb standby current (-5, -7) v cc = 1.9v, v ccio = 3.6v 100 a i ccsb standby current (-4) v cc = 1.9v, v ccio = 3.6v ma i cc dynamic current (-5, -7) f = 1 mhz ma f = 50 mhz ma i cc dynamic current (-4) f = 1 mhz ma f = 50 mhz ma c jtag jtag input capacitance f = 1 mhz pf c clk global clock input capacitance f = 1 mhz pf c io i/o capacitance f = 1 mhz pf
xc2c64 coolrunner-ii cpld 4 www.xilinx.com ds092 (v1.2) may 13, 2002 1-800-255-7778 advance product specification r lvcmos 3.3v dc voltage specifications lvcmos 2.5v dc voltage specifications symbol parameter test conditions min. max. units v ccio input source voltage 3.0 3.6 v v ih high level input voltage 2 v ccio + 0.3v v v il low level input voltage ?0.3 0.8 v v oh high level output voltage i oh = ?8 ma, v ccio = 3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 3v - 0.4 v i ol = 0.1 ma, v ccio = 3v - 0.2 v i il input leakage current v in = 0v or v ccio to 3.9v ?10 10 a i ih i/o high-z leakage v in = 0v or v ccio to 3.9v ?10 10 a c jtag jtag input capacitance f = 1 mhz pf c clk global clock input capacitance f = 1 mhz pf c io i/o capacitance f = 1 mhz pf symbol parameter test conditions min. max. units v ccio input source voltage 2.3 2.7 v v ih high level input voltage 1.7 3.9 v v il low level input voltage ?0.3 0.7 v v oh high level output voltage i oh = ?8 ma, v ccio = 2.3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 2.3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 2.3v - 0.4 v i ol = 0.1ma, v ccio = 2.3v - 0.2 v i il input leakage current v in = 0v or v ccio to 3.9v ?10 10 a i ih i/o high-z leakage v in = 0v or v ccio to 3.9v ?10 10 a c jtag jtag input capacitance f = 1 mhz pf c clk global clock input capacitance f = 1 mhz pf c io i/o capacitance f = 1 mhz pf
xc2c64 coolrunner-ii cpld ds092 (v1.2) may 13, 2002 www.xilinx.com 5 advance product specification 1-800-255-7778 r lvcmos 1.8v dc voltage specifications 1.5v dc voltage specifications (1) symbol parameter test conditions min. max. units v ccio input source voltage 1.7 1.9 v v ih high level input voltage 0.7 x v ccio 3.9 v v il low level input voltage ?0.3 0.2 x v ccio v v oh high level output voltage i oh = ?8 ma, v ccio = 1.7v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.7v v ccio ? 0.2 - v v ol low level output voltage i ol = 8 ma, v ccio = 1.7v - 0.45 v i ol = 0.1 ma, v ccio = 1.7v - 0.2 v i il input leakage current v in = 0 or v ccio to 3.9v ?10 10 a i ih i/o high-z leakage v in = 0 or v ccio to 3.9v ?10 10 a c jtag jtag input capacitance f = 1 mhz pf c clk global clock input capacitance f = 1 mhz pf c io i/o capacitance f = 1 mhz pf symbol parameter test conditions min. max. units v ccio input source voltage 1.4 1.6 v v ih high level input voltage 0.7 x v ccio 3.9 v v il low level input voltage ?0.3 0.3 v v oh high level output voltage i oh = ?4 ma, v ccio = 1.4v v ccio ? 0.45 v i oh = ?0.1 ma, v ccio = 1.4v v ccio ? 0.2 v v ol low level output voltage i ol = 8 ma, v ccio = 1.4v 0.4 v i ol = 0.1 ma, v ccio = 1.4v 0.2 v i il input leakage current v in = 0 or v ccio to 3.9v ?10 10 a i ih i/o high-z leakage v in = 0 or v ccio to 3.9v ?10 10 a c jtag jtag input capacitance f = 1 mhz pf c clk global clock input capacitance f = 1 mhz pf c io i/o capacitance f = 1 mhz pf notes: 1. hysteresis used on 1.5v inputs.
xc2c64 coolrunner-ii cpld 6 www.xilinx.com ds092 (v1.2) may 13, 2002 1-800-255-7778 advance product specification r ac electrical characteristics over recommended operating conditions symbol parameter -4 -5 -7 units min. max. min. max. min. max. t pd1 propagation delay single p-term - 3.7 - 4.6 - 6.7 ns t pd2 propagation delay or array - 4.0 - 5.0 - 7.5 ns t suf fast input register p-term clock setup time 1.6 - 1.9 - 2.3 - ns t su1 setup time fast (single p-term) 1.7 - 2.0 - 2.5 - ns t su2 setup time (or array) 2.0 - 2.4 - 3.3 - ns t hf fast input register hold time 0 - 0 - 0 - ns t h p-term hold time 0 - 0 - 0 - ns t co clock to output - 3.0 - 3.9 - 6.0 ns f toggle (1) internal toggle rate - 416 - 250 - 168 mhz f system1 (2) maximum system frequency - 294 - 233 - 159 mhz f system2 (2) maximum system frequency - 270 - 213 - 141 mhz f ext1 (3) maximum external frequency - 213 - 169 - 118 mhz f ext2 (3) maximum external frequency - 200 - 159 - 108 mhz t psuf fast input register p-term clock setup time 1.0 - 1.2 - 1.5 - ns t psu1 p-term clock setup time (single p-term) 1.0 - 1.2 - 1.5 - ns t psu2 p-term clock setup time (or array) 1.4 - 1.7 - 2.5 - ns t phf fast input register p-term clock hold time 0.4 - 0.6 - 0.7 - ns t ph p-term clock hold 0.3 - 0.5 - 0.5 - ns t pco p-term clock to output - 3.6 - 4.6 - 6.8 ns t oe /t od global oe to output enable/disable - 3.9 - 4.9 - 7.0 ns t poe /t pod p-term oe to output enable/disable - 4.3 - 5.3 - 7.3 ns t moe /t mod macrocell driven oe to output enable/disable - 4.9 - 6.3 - 9.2 ns t pao p-term set/reset to output valid - 5.4 - 6.4 - 9.1 ns t ao global set/reset to output valid - 5.5 - 6.5 - 9.3 ns t suec register clock enable setup time 1.8 - 2.1 - 2.6 - ns t hec register clock enable hold time 0 - 0 - 0 - ns t cw global clock pulse width high or low 1.2 - 2.0 - 3.0 - ns t pcw p-term pulse width high or low 4.0 - 5.0 - 7.5 - ns t config configuration time s notes: 1. f toggle (1/2*t cw ) is the maximum frequency of a dual edge triggered t flip-flop with output enabled. 2. f system1 (1/t cycle ) is the internal operating frequency for a device fully populated with 16-bit resettable binary counter through one p-term per macrocell while f system2 is through the or array (one counter per function block). 3. f ext1 (1/t su2 +t co ) is the maximum external frequency using one p-term while f ext2 is through the or array.
xc2c64 coolrunner-ii cpld ds092 (v1.2) may 13, 2002 www.xilinx.com 7 advance product specification 1-800-255-7778 r internal timing parameters symbol parameter (1) -4 -5 -7 units min. max. min. max. min. max. buffer delays t in input buffer delay - 1.3 - 1.7 - 2.4 ns t fin fast data register input delay - 1.6 - 2.1 - 3.0 ns t gck global clock buffer delay - 1.2 - 1.6 - 2.5 ns t gsr global set/reset buffer delay - 1.9 - 2.4 - 3.5 ns t gts global 3-state buffer delay - 1.4 - 1.9 - 3.0 ns t out output buffer delay - 1.6 - 1.9 - 2.8 ns t en output buffer enable/disable delay - 2.5 - 3.0 - 4.0 ns p-term delays t ct control term delay - 0.5 - 0.6 - 0.9 ns t logi1 single p-term delay adder - 0.4 - 0.5 - 0.8 ns t logi2 multiple p-term delay adder - 0.3 - 0.4 - 0.8 ns macrocell delay t pdi input to output valid - 0.4 - 0.5 - 0.7 ns t sui setup before clock 1.2 - 1.4 - 1.8 - ns t hi hold after clock 0 - 0 - 0 - ns t ecsu enable clock setup time 1.2 - 1.4 - 1.8 - ns t echo enable clock hold time 0 - 0 - 0 - ns t coi clock to output valid - 0.2 - 0.4 - 0.7 ns t aoi set/reset to output valid - 2.0 - 2.2 - 3.0 ns t cdbl clock doubler delay - 0 - 0 - 0 ns feedback delays t f feedback delay - 1.6 - 2.0 - 3.0 ns t oem macrocell to global oe delay - 1.0 - 1.3 - 2.0 ns i/o standard time adder delays 1.5v i/o t in15 standard input adder - 0.5 - 0.8 - 1.0 ns t hys15 hysteresis input adder - 2.0 - 3.0 - 4.0 ns t out15 output adder - 0.5 - 0.8 - 1.0 ns t slew15 output slew rate adder - 2.0 - 3.0 - 4.0 ns i/o standard time adder delays 1.8v cmos t in18 standard input adder - 0 - 0 - 0 ns t hys18 hysteresis input adder - 2.0 - 3.0 - 4.0 ns t out18 output adder - 0 - 0 - 0 ns t slew output slew rate adder - 2.0 - 3.0 - 4.0 ns
xc2c64 coolrunner-ii cpld 8 www.xilinx.com ds092 (v1.2) may 13, 2002 1-800-255-7778 advance product specification r switching characteristics i/o standard time adder delays 2.5v cmos t in25 standard input adder - 0.5 - 0.8 - 1.0 ns t hys25 hysteresis input adder - 1.5 - 2.5 - 3.0 ns t out25 output adder - 1.5 - 2.5 - 3.0 ns t slew25 output slew rate adder - 2.0 - 3.0 - 4.0 ns i/o standard time adder delays 3.3v cmos/ttl t in33 standard input adder - 0.7 - 1.0 - 2.0 ns t hys33 hysteresis input adder - 1.0 - 2.0 - 3.0 ns t out33 output adder - 1.0 - 2.0 - 3.0 ns t slew33 output slew rate adder - 2.0 - 3.0 - 4.0 ns notes: 1. 1.5 ns input pin signal rise/fall. internal timing parameters (continued) symbol parameter (1) -4 -5 -7 units min. max. min. max. min. max. number of outputs switching 1 2 4 8 12 16 4.0 4.4 5.8 v cc = 1.8v, 25 o c t pd_pal (ns) 6.0 5.6 4.2 ds092_09_121501
xc2c64 coolrunner-ii cpld ds092 (v1.2) may 13, 2002 www.xilinx.com 9 advance product specification 1-800-255-7778 r notes: 1. gts = global output enable, gsr = global set reset, gck = global clock x pin descriptions function block macro- cell pc44 vq44 cp56 vq100 1 1 44 38 f1 13 1 2 43 37 e3 12 1 3 42 36 e1 11 14---10 15---9 16---8 17---7 18---6 1(gts1) 9 40 34 d1 4 1(gts0) 10 39 33 c1 3 1(gts3) 11 38 32 a3 2 1(gts2)123731a21 1(gsr) 13 36 30 b1 99 114--a197 115--c394 116---92 21139g114 22240f315 23---16 24---17 25341h118 26442g319 2(gck0) 7 5 43 j1 22 2(gck1) 8 6 44 k1 23 29--k424 2(gck2) 10 7 1 k2 27 211---28 21282k329 21393h330 214--k532 215---33 216---34 3 1 35 29 c4 91 3 2 34 28 a4 90 3 3 33 27 c5 89 34--a781 35--c879 3 6 29 23 a8 78 37--a977 38---76 39--a574 3102822a1072 3112721b1071 3 12 26 20 c10 70 313--d868 3142519e867 3 15 24 18 d10 64 316---61 41115k635 42126h536 43--k737 44---39 45--h740 46---41 47148h842 48---43 49---49 410--k850 4 11 18 12 h10 52 412---53 4131913g1055 4142014-56 4152216f1058 416--e1060 pin descriptions (continued) function block macro- cell pc44 vq44 cp56 vq100
xc2c64 coolrunner-ii cpld 10 www.xilinx.com ds092 (v1.2) may 13, 2002 1-800-255-7778 advance product specification r xc2c64 global, jtag, powe r/ground and no connect pins ordering information pin type pc44 vq44 cp56 vq100 tck 17 11 k10 48 tdi 15 9 j10 45 tdo 30 24 a6 83 tms 16 10 k9 47 v aux (jtag supply voltage) 41 35 d3 5 power internal (v cc ) power external i/o (v ccio ) 21 15 g8 26,57 13, 32 7,26 h6, c6 38, 51,88, 98 ground 10,23,31 4,17,25 h4, f8, c7 21,31,62,69,84,100 no connects 20,25,44,46,54,59,63,65,66,73,75, 80,82,85,86,87,93,95,96 total user i/o 33 33 45 64 device ordering no. and part marking no. pin/ball spacing ja (c/watt) jc (c/watt) package type package dimensions i/o comm. (c) ind. (i) xc2c64-4pc44c 1.27mm 53.1 28.7 plastic leaded chip carrier 17.5mm x 17.5mm 33 c XC2C64-5PC44C 1.27mm 53.1 28.7 plastic leaded chip carrier 17.5mm x 17.5mm 33 c xc2c64-7pc44c 1.27mm 53.1 28.7 plastic leaded chip carrier 17.5mm x 17.5mm 33 c xc2c64-4vq44c 0.8mm 46.6 8.2 very thin quad flat pack 12mm x 12mm 33 c xc2c64-5vq44c 0.8mm 46.6 8.2 very thin quad flat pack 12mm x 12mm 33 c xc2c64-7vq44c 0.8mm 46.6 8.2 very thin quad flat pack 12mm x 12mm 33 c xc2c64-4cp56c 0.5mm 65.0 15.0 chip scale package 6mm x 6mm 45 c xc2c64-5cp56c 0.5mm 65.0 15.0 chip scale package 6mm x 6mm 45 c xc2c64-7cp56c 0.5mm 65.0 15.0 chip scale package 6mm x 6mm 45 c xc2c64-4vq100c 0.5mm 53.2 14.6 very thin quad flat pack 14mm x 14mm 64 c xc2c64-5vq100c 0.5mm 53.2 14.6 very thin quad flat pack 14mm x 14mm 64 c xc2c64-7vq100c 0.5mm 53.2 14.6 very thin quad flat pack 14mm x 14mm 64 c xc2c64-7pc44i 1.27mm 53.1 28.7 plastic leaded chip carrier 17.5mm x 17.5mm 33 i xc2c64-7vq44i 0.8mm 46.6 8.2 very thin quad flat pack 12mm x 12mm 33 i xc2c64-7cp56i 0.5mm 65.0 15.0 chip scale package 6mm x 6mm 45 i xc2c64-7vq100i 0.5mm 53.2 14.6 very thin quad flat pack 14mm x 14mm 64 i
xc2c64 coolrunner-ii cpld ds092 (v1.2) may 13, 2002 www.xilinx.com 11 advance product specification 1-800-255-7778 r figure 2: pc44 package pc44 to p v i e w i/o (1) i/o (1) i/o (1) i/o (3) i/o i/o i/o v ccio gnd tdo i/o i/o (2) i/o (2) i/o i/o i/o i/o i/o i/o i/o v aux i/o (1) i/o i/o i/o v cc i/o gnd i/o i/o i/o i/o i/o i/o (2) i/o i/o gnd i/o i/o v ccio i/o tdi tms tck 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 6 5 4 3 2 1 44 43 42 41 40 (1) - global output enable (2) - global clock (3) - global set/reset figure 3: vq44 package vq44 top view i/o (1) i/o (1) i/o (1) i/o (3) i/o i/o i/o v ccio gnd tdo i/o i/o (2) i/o (2) i/o i/o i/o i/o i/o i/o i/o v aux i/o (1) i/o i/o i/o v cc i/o gnd i/o i/o i/o i/o i/o i/o (2) i/o i/o gnd i/o i/o v ccio i/o tdi tms tck 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 (1) - global output enable (2) - global clock (3) - global set/reset figure 4: cp56 package cp56 bottom view i/o (2) i/o (2) i/o i/o i/o i/o i/o i/o tms tck i/o (2) tdi i/o i/o gnd i/o v ccio i/o i/o i/o i/o i/o v cc i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o (1) v aux i/o i/o i/o (1) i/o i/o i/o v ccio gnd i/o i/o i/o (3) i/o i/o i/o (1) i/o (1) i/o i/o tdo i/o i/o i/o i/o k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 (1) - global output enable (2) - global clock (3) - global set/reset
xc2c64 coolrunner-ii cpld 12 www.xilinx.com ds092 (v1.2) may 13, 2002 1-800-255-7778 advance product specification r revision history the following table shows the revision history for this document. figure 5: vq100 package date version revision 01/03/02 1.0 initial xilinx release. 03/04/02 1.1 removed a4 from the fb1, mc16, and cp56 in the pinout tables. updated v oh and v ol for lvcmos 2.5v, lvcmos 1.8v, and 1.5v dc voltage specifications. 05/13/02 1.2 removed fast industrial speed grade. updated 1.5 dc voltage, v oh parameter from i oh = ?0.8 ma to ?0.4 ma. updated ac electrical characteristics and added new parameters vq100 top view gnd i/o (3) v ccio i/o nc nc i/o nc i/o i/o i/o i/o v ccio nc nc nc gnd tdo nc i/o nc i/o i/o i/o i/o v cc i/o (2) i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o v ccio i/o i/o i/o i/o i/o nc tdi nc tms tck i/o i/o nc i/o nc i/o i/o i/o gnd i/o i/o nc nc i/o nc gnd i/o i/o nc i/o vcc i/o i/o nc i/o i/o v ccio i/o (1) i/o (1) i/o (1) i/o (1) v aux i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o nc gnd i/o (2) i/o (2) i/o nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (1) - global output enable (2) - global clock (3) - global set/reset

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